Semiconductor dynamic memory

ABSTRACT

A semiconductor dynamic memory including a plurality of functional blocks or interface circuits for controlling the memory, such as a row-enable buffer, a row-address buffer, a word decoder, a column-enable buffer, a column-address buffer, and a column decoder. The functional blocks in the semiconductor dynamic memory are sequentially reset by signals from the subsequent functional block so that the power operations of the functional blocks of the subsequent stages is indicated by the reset signal, and thus are returned to the state in which they are ready to execute the next processing.

FIELD OF THE INVENTION

The present invention relates to a semiconductor dynamic memory which iscapable of reducing a cycle time.

BACKGROUND OF THE INVENTION

The dynamic memory essentially requires a reset period. In theconventional dynamic memory in which all of the portions are reset atone time, the cycle time is the sum of a period (access time) includingfrom the start of access of a portion to which the access is made atfirst to the completion of access of a portion to which the access isfinally made and a reset time. On the other hand, the static memory doesnot require resetting. Therefore, the cycle time of the static memory isnearly equal to the access time. Thus, the dynamic memory having a longcycle time is capable of writing and reading data in a quantity smallerthan that of the static memory within a unit period of time.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor dynamicmemory which removes the drawbacks in the conventional dynamic memory.

Another object of the present invention is to provide a semiconductordynamic memory which is capable of reducing a cycle time.

A further object of the present invention is to provide a semiconductordynamic memory having a cycle time which is equal to, or shorter than,an access time.

For achieving the above mentioned object, the present invention dealswith a semiconductor dynamic memory comprising a plurality of functionalblocks interface circuits such as a row-enable buffer, a row addressbuffer which receives the output signal from the row enable buffer, aword decoder which is connected to the row address buffer, a group ofsense amplifiers which are coupled to word lines connected to the worddecoder, a column enable buffer, a column address buffer which receivesthe output signal from the column enable buffer, a column decoder whichreceives the column address signal from the column address buffer andwhich selects one of the sense amplifiers, a data buffer which receivesthe output of the selected sense amplifier, and an output buffer whichis connected to the data buffer. At least one of the functional blocksis reset to be ready to execute the next processing by a signal which isprovided from a subsequent functional block and proves that thesubsequent function block has begun its operation.

Further features and advantages of the present invention will beapparent from the ensuing description with reference to the accompanyingdrawings to which, however, the scope of the invention is in no waylimited.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are a block diagram and a time chart illustrating theconstruction and operation of a major portion of a conventional dynamicmemory;

FIGS. 3 and 4 are a block diagram and a time chart illustrating anembodiment and operation according to the present invention;

FIGS. 5 and 6 are a diagrams illustrating in detail the row-enablebuffer circuit of FIG. 3 and waveforms for illustrating its operation;

FIG. 7 is a diagram illustrating in detail the word decoder, the senseamplifiers, the column decoder and the writing system circuit shown inFIG. 3;

FIGS. 8A, 8B and 8C are diagrams illustrating in detail the columndecoder, the buffer data and the output buffer shown in FIG. 3; and

FIGS. 9A, 9B and 9C are diagrams illustrating waveforms for illustratingthe operation of the circuit shown in FIGS. 8A, 8B and 8C.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 and 2 illustrate the construction and operation of a majorportion (peripheral circuit) of the interface circuit of theconventional most generally employed dynamic memory. As an invertedsignal RAS of a row-address strobe assumes the L (low) level, thecircuit in the row system commences to operate, and the row-enablebuffer (REB)1, row-address buffer (RAB)2 and word decoder (WD)3 produceoutputs RE, RA and WL, successively. Then, as an inverted signal CAS ofthe column-address strobe assumes the L level, the column systemcommences to operate, whereby the column-enable buffer (CEB)4,column-address buffer (CAB)5 and column decoder (CD)6 produce outputsCE, CA and D, successively. Here, one of the outputs BD of the senseamplifiers 7 produced by the operation of the row system is selected bythe column decoder 6, and is converted into a data out DO via databuffer (DB)8 and output buffer (OB)9. At the time when the operation ofthe output buffer (OB)9 is finished, the inverted signals RAS and CASassume the H (high) level. Therefore, the row-enable buffer (REB)1 andcolumn-enable buffer (CEB)4 produce reset signals RE and CE, so that therow enable buffer (RAB), the word decoder (WD), . . . the column addressbuffer (CAB) and the column decoder (CD) . . . are reset at one time. InFIG. 2, time axis numerals 0, 50, 100, . . . at the upper most linerepresent the lapse of time in unit of nanoseconds. According to thisembodiment, therefore, the cycle time is 270 nanoseconds. On the otherhand, the time t_(RAC) from the start of access to a moment at which theread data RD is produced is 150 nanoseconds. Therefore, the cycle timeis considerably longer than the time t_(RAC).

FIGS. 3 and 4 illustrate the construction and operation of the interfacecircuits of the a major portion of memory according to the presentinvention. As illustrated in the diagrams, the individual portionsaccording to the present invention are reset immediately after theoperation is finished, and are ready to start the next operation. Thatis, the functional blocks are reset as soon as the subsequent block hasbegun operation and captured the signal. Namely, the row system andcolumn system commence the operation when the inverted signals RAS andCAS assume the L level. Here, however, the row-enable buffer (REB)11 isimmediately reset by a signal which is caused by the operation of therow-address buffer (RAB)12. The same also holds true for the row-addressbuffer (RAB)12 and column-enable buffer (CEB)14, without the need ofwaiting for the return of signals RAS and CAS. Therefore, when the resetis finished, the individual portions enter again into the active periodand perform the next operation. Consequently, the cycle time becomesequal to the sum of the active period and the reset time, and is greatlyreduced. Although it is difficult to perform the read-modify-writeoperation, the cycle time is so shortened that there practically arisesno problem. Further, the dynamic memory which performs the addressmultiplex operation, must latch a row address as well as a columnaddress, and hence necessitates two clock signals RAS and CAS. If acolumn address is latched by utilizing the rise in the clock signal RAS,however, the clock signal CAS need not be employed.

When the writing operation is taken into consideration, the word decoder(WD)13 must be reset after the completion of the operation of the columndecoder (CD)16 which is a block of the next but one stage (the secondstage--the first one is skipped). Further, the output buffer (OB)19which generates read data to the output terminal D_(out) receives areset signal from the column decoder 16 when the column decoder 16commences operation, starts the resetting operation, and completes theresetting operation while the data buffer (DB)18 is being operated.Thus, with the output buffer 19 being reset, it is possible to retainthe read data of the previous cycle up to a moment just before a newread data is produced. In this case, the read data is maintained at theoutput terminal at all times, and therefore it is not allowed tocommonly utilize the output terminal for another memory or to connectthe output terminal in parallel with another memory. The output terminalcan be connected in parallel with another memory if a chip selectcircuit (CSC)21 is provided and the output buffer 19 is controlled bythe output signal CS. In FIG. 3, reference numeral 20 (WSC) denotes acircuit of the writing system, a signal WE denotes an invertedwrite-enable signal, and a signal D_(IN) denotes a writing data. Thetime axis numerals 0, 50, 100 . . . shown at the upper most line of FIG.4 denote the lapse of time (in nano-second units). The time t_(RAC) fromthe first access to a moment at which the read data is produced is 150nanoseconds, the same as the conventional memory shown in FIG. 2. On theother hand, the row enable buffer (REB)11 commences the reset at thetime 40 nanoseconds and said reset is completed at the time 100nanoseconds, so that at the time 100 NS the operation of the next cyclecan be carried out. Therefore, one cycle can be completed during 100nanoseconds. Further, the functional blocks other than the row enablebuffer (REB)11 can complete similarly one cycle during 100 nanoseconds.Therefore, the memory can be operated with the cycle time of 100nanoseconds. This cycle time of 100 nanoseconds is more rapid than thatof the conventional memory which requires the cycle time of 270nanoseconds, so that the function of the memory in the present inventionis greatly improved.

FIGS. 5 and 6 illustrate a circuit and timings with regard to therow-enable buffer (REB)11. Symbols Q₁ to Q₁₄ denote MOS transistors orMOS capacitors, and N₁ to N₅ denote nodes or potentials at the nodes.When the inverted signal RAS assumes the low level, the node N₂ assumesthe high level, the transistors Q₇ and Q₈ are rendered conductive, thenode N₄ assumes the high level, the node N₃ assumes the low level, thetransistors Q₁₀ and Q₁₃ are rendered conductive, the transistors Q₁₂ andQ₁₄ are rendered non-conductive, and the node N₅ and output RE assumethe high level. When the output RE assumes the high level, therow-address buffer (RAB)12 operates to produce the output signal RA ofthe high level. The signal RA is fed back to the row-enable buffer(REB)11 in FIG. 5, whereby the transistors Q₅, Q₆ and Q₉ are renderedconductive, the node N₂ assumes the low level, the transistors Q₇ andQ.sub. 8 are rendered non-conductive, the node N₃ assumes the highlevel, the node N₄ assumes the low level, the transistors Q₁₀ and Q₁₃are rendered non-conductive, the transistors Q₁₂ and Q₁₄ are renderedconductive, and the node N₅ and the output RE assume the low level.Here, since the signal RA is reset by the completion of the operation ofword decoder (WD)13, the inverted signal RAS must be assumed to be highlevel before the signal RA is reset. If the inverted signal RAS ismaintained at the low level, the row-enable buffer (REB)11 commences thenext operation when the signal RA is reset.

FIG. 7 illustrates a circuit including the word decoder 13, the columndecoder 16, the sense amplifier 17, the data buffer 18 and the writingsystem circuit 20 in FIG. 3. As seen from FIG. 3, almost all functionalblocks receive the reset signal from the next functional block, however,the word decoder (WD)13 should receive the reset signal after the timewhen the function of the column decoder is completed. Next we willexplain the reason why the word decoder (WD)13 should receive the resetsignal from the column decoder which is a block of the next but onestage. As illustrated in FIG. 7, the sense amplifier 17 in FIG. 3 isformed by a group of sense amplifiers 17a, . . . , 17n, the columndecoder 16 in FIG. 3 is formed by a group of column decoders 16a, . . ., 16n and the write system circuit 20 includes a writing circuit 20a anda buffer amplifier which includes transistors Q₂₁, Q₂₂, Q₂₃ and Q₂₄. Inthe circuit shown in FIG. 7, the output WL1, . . . , WLm of the worddecoder are coupled via memory cells MC and bit lines BL1, . . . , BLnto the sense amplifiers 17a, . . . , 17n. The column decoder 16a, . . ., 16n receives the output (BD₁, BD₁, . . . , BD_(n), BD_(n)) from thesense amplifiers 17a, . . . , 17n and the output signal CA from thecolumn address buffer 15, and the output signal of the column decoder16a, . . . , 16n are coupled via data lines DL and DL to the data buffer18. In the reading operation, the word decoder (WD)13 selects one of theword lines WL₁ ˜WL_(2m) and the data of the memory cells which areconnected to the selected word line are transmitted to the bit lines andamplified by the sense amplifiers SA₁ ˜SA_(n), and only the data whichis selected by the column decoder CD₁ ˜CD_(n) is transmitted to thelines DL and DL. When the reading operation is carried out in such amanner, the word decoder (WD)13 can be reset after the data of thememory cells are transmitted to the bit lines and amplified by the senseamplifiers. Therefore, it is not necessary to await the operation of thecolumn decoder (CD)16 when executing the reading operation.Contrariwise, in the writing operation, the data which is written in thelines DL and DL by the writing system circuit 20 is written via thecolumn decoder sense amplifiers and the bit lines in the memory cellwhich is selected by the word lines. Therefore, the word lines can notbe reset till the time when the column decoder is operated and the datais written in the memory cells via the lines DL and DL and the bitlines. This is the reason why the word decoder (WD)13 receives the resetsignal from the column decoder (CD)16.

As shown in FIG. 3, different from the other blocks or interfacecircuits, the output buffer (OB)19 receives the reset signal from thecolumn decoder 16 which is two stages from the output buffer 19. This isdue to the reason that the read data is maintained at the outputterminal D_(out) till the next data is output at said output terminalD_(out). If it is not necessary to output the data before the next datais output, the chip select circuit (CSC)21 may control the output buffer(OB)19 so as to disable the output D_(out). For the purpose ofexplaining the method for resetting the output buffer (OB)19, a moredetailed functional block diagram of the column decoder, the data bufferand the output buffer are shown in FIGS. 8A˜8C.

The column decoder 16 shown in FIG. 3 includes a column decoder driver16a and a column decoder 16b as shown in FIG. 8A, the data buffer 18shown in FIG. 3 includes a data buffer driver 18a and a data buffer 18bas shown in FIG. 8A, and the output buffer 19 shown in FIG. 3 includesan output buffer driver 19a and an output buffer 19b. The reset signalis supplied from the column decoder driver 16a to the word decoder 13,the sense amplifier 17 and the writing system circuit, the data bufferdriver 18a generates a reset signal for the column decoder driver 16aand the column decoder 16b. The reset of the output buffer 19 iscommenced by the output signal CDD of the column decoder driver 16a. Onthe other hand, the data buffer 18 commences operation by the signalCDD, so that the output buffer driver 18b is reset during the operationof the data buffer 18b. When the output buffer driver 18b is reset, theoutput OBD of the output buffer driver 18b is also reset so that theoutput buffer 19b is reset at the same time. The output buffer driver19a and the output buffer 19b are competely reset till the time when thedata buffer driver 18b outputs the output signal DBD. Therefore, theoutput buffer 19b can receive the signal DBD and the read data RD andRD, so that the output buffer 19 commences operation and supplies theread data at the output terminal D_(out). At the same time when theoperation of the output buffer driver 19a is completed, the signal DBRis generated so as to reset the data buffer 18. This signal DBR isautomatically reset by the timing circuit included in the output bufferdriver 19a at about the time when the data buffer 18 is completely resetby the signal DBR. On the other hand, the output signal OBD of theoutput buffer driver 19a is maintained till the time when the outputbuffer driver receives the signal CDD in the next cycle so that the readdata is maintained at the output terminal D_(out).

FIG. 8B is a circuit of the output buffer driver 19a, symbols Q₃₁through Q₅₂ denote MOS transistors or MOS capacitors and symbols N₁₁through N₁₉ denote nodes or potentials at the nodes. The circuit whichis formed by the transistors Q₃₁ ˜Q₄₂ is the circuit which forms thesignal OBD. The timing chart of this circuit is shown in FIG. 9A. Atfirst, when the signal CDD is placed in the high level, the potential inthe nodes N₁₂ and N₁₃ is placed in the high level and the potential inthe node N₁₄ is placed in the low level so that this circuit is reset,the transistor Q₄₁ is placed in the off state, the transistor Q₄₂ isplaced in the on state and the signal OBD is placed in the low levelstate. After the reset is completed, at the time t₂, the signal DBD isplaced in the high level and the signal CDD is placed in the low levelso that this circuit commences operation.

When node N₁₄ is placed in the high level and the node N₁₂ is placed inthe low level, the transistor Q₄₁ is placed in the on state, thetransistor Q₄₂ is in the off state, the signal OBD is placed in the highlevel so that the output buffer 19b is driven.

The circuit which includes the transistors Q₄₃ ˜Q₅₂ and the resistor R₆₁is the circuit for forming the signal DBR and the timing chart of thiscircuit is shown in FIG. 9B. This circuit is reset by the signal CDD.After this circuit is reset, when the signal OBD is placed in the highlevel, the signal DBR is also placed in the high level. Thereafter, thenode N₁₈ is placed in the high level by the timing circuit including thetransistors Q₄₃ ˜Q₄₈ and the resistor R₆₁. Therefore, the transistor Q₅₀is placed in the on state, the node N₁₉ is placed in the low level andthe transistor Q₅₁ is placed in the off state. On the other hand, thetransistor Q₅₂ is placed in the on state so that the signal DBR isplaced at the low level via the transistor Q₅₂. FIG. 8C is a circuit ofthe output buffer 19b, symbols Q₆₁ through Q₆₈ denotes MOS transistorsand symbols N₂₁ through N.sub. 24 denote nodes or potentials at thenodes. The time chart of the output buffer 19b is shown in FIG. 9C. Atthe time t₁, the node N₂₃ is placed at the high level and the transistorQ₆₇ is placed in the on state therefore the high level is output at theoutput terminal D_(out). At the time t₂, the signal OBD is placed in thelow level, the potential of node N₂₃ is discharged via the transistorQ₆₃ to the signal OBD, the transistor Q₆₇ is placed in the off state andis reset. At the time t₃, the potential levels of the nodes N₂₁ and N₂₂are determined by the signal RD, RD. That is, one of the nodes N₂₁ andN₂₂ is placed at the high level and another of them is placed in the lowlevel. In the example shown in FIG. 9C, the node N₂₂ is in the highlevel and the node N₂₁ is in the low level. Thereafter, when the signalOBD is placed at the high level, as the transistor Q₆₄ is in the onstate, the node N₂₄ is placed in the high level, so that the transistorQ₆₃ is placed in the on state. On the other hand, if the signal OBD isplaced in the high level, the transistor Q₆₃ is in the off state,therefore, the node N₂₃ is maintained at the low level and thetransistor Q₆₇ is in the off state. Therefore, the output D_(out) isplaced in the low level state.

According to the present invention as illustrated in the foregoing, theindividual functional blocks or interface circuits (except the outputbuffer) which have finished the operation, are readily reset by thesignals of functional block of the next stage or of the next but onestage. And, the output buffer which maintains last read data on terminalD_(out) is reset with a signal from the column decoder just before theoutput buffer commences the new operation. Therefore, it is possible togreatly reduce the cycle time of the dynamic memory and, eventually, towrite and read large amounts of data within reduced periods of time.

I claim:
 1. A semiconductor dynamic memory comprising a plurality ofinterface circuits including:a row-enable buffer for generating a rowenable output signal; a row address buffer, operatively connected toreceive the row enable output signal from said row enable buffer; a worddecoder operatively connected to said row address buffer; word linesoperatively connected to said word decoder; a group of sense amplifiers,operatively connected to said word lines, for generating a sense outputsignal; a column enable buffer for generating a column enable outputsignal; a column address buffer, operatively connected to receive thecolumn enable output signal from said column enable buffer, forgenerating a column address signal in dependence upon the column enableoutput signal; a column decoder operatively connected to receive thecolumn address signal from said column address buffer and which columnaddress signal selects one of said sense amplifiers; a data bufferoperatively connected to receive the sense output signal of the selectedsense amplifier; and an output buffer operatively connected to said databuffer, at least one of said interface circuits being reset, so as to beready to execute the next processing, by a reset signal which isgenerated by a connected interface circuit which receives an outputsignal generated by the at least one interface circuit and the resetsignal proves that said connected interface circuit has begun itsoperation.
 2. A semiconductor dynamic memory according to claim 1,wherein said row address buffer and said word decoder generate first andsecond signals, wherein said row enable buffer is reset by the firstsignal generated by said row address buffer, and said row address bufferis reset by the second signal generated by said word decoder.
 3. Asemiconductor dynamic memory according to claim 1 or 2, wherein saidcolumn decoder generates a third signal, wherein both said word decoderand said sense amplifier are reset by the third signal generated by saidcolumn decoder.
 4. A semiconductor dynamic memory according to claim 1or 2, wherein said column decoder generates a fourth signal, whereinsaid output buffer is reset by the fourth signal generated by saidcolumn decoder.
 5. A semiconductor dynamic memory according to claim 1or 2, wherein said semiconductor dynamic memory is operatively connectedto receive an external clock signal having a rising edge and a fallingedge, wherein said row-enable buffer commences operation in dependenceupon the rising edge or a falling edge of the external clock signal andsaid column-enable buffer commences operation in dependence upon thefalling edge or the rising edge of said external clock signal independence upon which edge of the external clock signal initiatesoperation of said row enable buffer.
 6. A semiconductor dynamic memoryaccording to claim 3, wherein column decoder generates a fourth signalwhich resets said output buffer.
 7. A semiconductor dynamic memoryaccording to claim 3 wherein said semiconductor dynamic memory isoperatively connected to receive an external signal having a rising edgeand a falling edge, wherein said row-enable buffer commences operationin dependence upon the rising edge or the falling edge of the externalclock signal and said column-enable buffer commences operation independence upon the falling edge or the rising edge of said externalclock signal in dependence upon which edge of the external clock signalinitiates operation of said row-enable buffer.
 8. A semiconductordynamic memory according to claim 4, wherein said semiconductor dynamicmemory is operatively connected to receive an external clock signalhaving a rising edge and a falling edge, wherein said row-enable buffercommences operation in dependence upon the rising edge or the fallingedge of the external clock signal and said column-enable buffercommences operation in dependence upon the falling edge or the risingedge of said external clock signal in dependence upon which edge of theexternal clock signal initiates operation of said row-enable buffer. 9.A semiconductor dynamic memory, operatively connectable to receive a rowaddress strobe signal, a column address strobe signal and a write enablesignal, comprising:a row-enable buffer, operatively connectable toreceive the row address strobe signal, for generating a first signal independence upon the row address strobe signal; a row address buffer,operatively connected to said row-enable buffer, for generating a firstreset signal and a second signal in dependence upon the first signal,said row-enable buffer being reset by the first reset signal; a worddecoder operatively connected to said row address buffer, for generatinga second reset signal and a third signal in dependence upon the secondsignal, said row address buffer being reset by the second reset signal;a sense amplifier, operatively connected to said word decoder, forgenerating a fourth signal in dependence upon the third signal; a columnenable buffer, operatively connectable to receive the column addressstrobe signal, for generating a fifth signal in dependence upon thecolumn address strobe signal; a column address buffer, operativelyconnected to said column enable buffer, for generating a third resetsignal and a sixth signal in dependence upon the fifth signal, saidcolumn enable buffer being reset by the third reset signal; a writingsystem circuit, operatively connectable to receive the write enablesignal, for generating a seventh signal in dependence upon the writeenable signal; a column decoder, operatively connected to said worddecoder, said sense amplifier, said column address buffer and saidwriting system circuit, for generating a fourth reset signal and aneighth signal in dependence upon the fourth, sixth and seventh signals,said word decoder, said sense amplifier, said column address buffer andsaid writing system circuit being reset by said fourth reset signal; adata buffer, operatively connected to said column decoder, forgenerating a fifth reset signal and a ninth signal in dependence uponthe eighth signal, said column decoder being reset by said fifth resetsignal; and an output buffer, operatively connected to said data bufferand said column decoder, for generating output data and a sixth resetsignal in dependence upon the ninth signal, said data buffer being resetby the sixth reset signal and said output buffer being reset by theeighth signal.
 10. A semiconductor dynamic memory as recited in claim 9,wherein said column strobe signal is the row address strobe signal. 11.A semiconductor dynamic memory according to claim 9 or 10, wherein saidsemiconductor dynamic memory is operatively connectable to receive achip select signal and further comprises a chip select circuit,operatively connectable to receive the chip select signal, forgenerating a tenth signal in dependence upon the chip select signal,wherein said output buffer generates the output data and the sixth resetsignal in dependence upon the ninth signal and the tenth signal.